This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to single-electron transistors and fabrication methods therefor.
Single-electron Transistor (SET) devices and fabrication methods are being widely investigated for high density and/or high performance microelectronic devices. As is well known to those having skill in the art, single-electron transistors use single-electron nanoelectronics that can operate based on the flow of single-electrons through nanometer-sized particles, also referred to as nanoparticles, nanoclusters or quantum dots. Although a single-electron transistor can be similar in general principle to a conventional Field Effect Transistor (FET), such as a conventional Metal Oxide Semiconductor FET (MOSFET), in a single-electron transistor, transfer of electrons may take place based on the tunneling of single-electrons through the nanoparticles. Single-electron transistors are described, for example, in U.S. Pat. Nos. 5,420,746; 5,646,420; 5,844,834; 6,057,556 and 6,159,620, and in publications by the present inventor Brousseau, III et al., entitled pH-Gated Single-Electron Tunneling in Chemically Modified Gold Nanoclusters, Journal of the American Chemical Society, Vol. 120, No. 30, 1998, pp. 7645-7646, and by Feldheim et al., entitled Self-Assembly of Single Electron Transistors and Related Devices, Chemical Society Reviews, Vol. 27, 1998, pp.1-12, and in a publication by Klein et al., entitled A Single-Electron Transistor Made From a Cadmium Selenide Nanocrystal, Nature, 1997, pp. 699-701, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
A major breakthrough in single-electron transistor technology is described in U.S. patent application Ser. No. 09/376,695, entitled Sensing Devices Using Chemically-Gated Single Electron Transistors, by Daniel L. Feldheim and the present inventor Louis C. Brousseau, III, also published as International Publication No. WO 01/13432 A1, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein. Described therein is a chemically-gated single-electron transistor that can be adapted for use as a chemical or biological sensor. Embodiments of these chemically-gated single-electron transistors include source and drain electrodes on a substrate and a nanoparticle between the source and drain electrodes, that has a spatial dimension of a magnitude of approximately 12 nm or less. An analyte-specific binding agent is disposed on a surface of the nanoparticle. A binding event occurring between a target analyte and the binding agent causes a detectable change in the characteristics of the single-electron transistor.
Notwithstanding these and other configurations of single-electron transistors, including chemically-gated single-electron transistors, it may be difficult to fabricate these devices using conventional photolithography that is employed to fabricate microelectronic devices. In particular, in order to provide quantum mechanical effects with nanoparticles, it may be desirable to provide spacing between the source and drain electrodes of a single-electron transistor that is less than about 20 nm, or less than about 12 nm or about 10 nm. It may be difficult, however, to provide these spacings using conventional lithography at low cost and/or with acceptable device yields.
Embodiments of the present invention provide single-electron transistors and manufacturing methods therefor, in which a projecting feature, such as a pyramid, projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. A desired spacing between the first and second electrodes therefore may be obtained without the need for high-resolution photolithography.
Embodiments of the present invention may stem from a realization that projecting features, such as pyramids, can be fabricated on a substrate, using conventional microelectronic fabrication techniques. The projecting feature, such as a pyramid, may have a small vertex. Thus, first and second electrodes that are formed on the projecting feature, adjacent the vertex, can have small spacing therebetween, such as less than about 20 nm or less than about 12 nm or about 10 nm, whereas it may be difficult to photolithographically define a region in a layer that is, for example, 10 nm wide. Accordingly, single-electron transistor devices may be fabricated using conventional microelectronic techniques, with the potential of low cost and/or high yields. It will be understood that, as used herein, the term xe2x80x9cvertexxe2x80x9d applies to a region on a surface of a pyramid where the sides of the pyramid intersect or approach one another. The vertex need not be the highest or lowest point of the pyramid.
Single-electron transistors according to other embodiments of the present invention comprise a substrate including a pyramid that projects from a face thereof. The pyramid includes a plurality of sides and an vertex. A first electrode is provided on a first side of the pyramid, including a first electrode end that extends adjacent the vertex. A second electrode is provided on the second side of the pyramid, and includes a second electrode end that extends adjacent the vertex and that is spaced apart from the first electrode end. At least one nanoparticle is provided on the vertex. In some embodiments, the first electrode end and the second electrode end are spaced apart by less than about 20 nm adjacent the vertex. In other embodiments, the first electrode end and the second electrode end are spaced apart by about 10 nm adjacent the vertex. In some embodiments, the vertex is a point, whereas in other embodiments, the vertex is a plateau (i.e. flat).
In some embodiments, the feature such as a pyramid projects outwardly, away from the face of the substrate, to provide a feature such as a pyramid that rises from the substrate face. In other embodiments, the feature such as a pyramid projects inwardly from the face of the substrate into the substrate, to provide a trench such as a pyramidal-shaped trench that extends into the substrate. In some embodiments, the pyramid includes four sides, and the first and second sides, on which the respective first and second electrodes are provided, are opposite one another.
In some embodiments, the first and second electrodes are free of nanoparticles thereon. In other embodiments, the at least one nanoparticle comprises a plurality of nanoparticles on the vertex, on the first electrode end, and/or on the second electrode end.
In other embodiments of the present invention, multiple single-electron transistors may be provided on a substrate, including a plurality of features such as pyramids, a plurality of first electrodes, and a plurality of second electrodes. At least one nanoparticle may be provided on the vertex of the pyramids. The first and second electrodes of adjacent transistors may be electrically connected together. Stated differently, an electrode may be provided that extends from a side of a pyramid to a side of an adjacent pyramid.
In yet other embodiments, a self-assembled monolayer, a polymer layer and/or other anchoring layer may be provided on the vertex, and the at least one nanoparticle may be provided on the anchoring layer, opposite the vertex. In other embodiments, the anchoring layer also may be provided on the first electrode end and on the second electrode end. In still other embodiments, an insulating layer may be provided on the vertex.
Some embodiments of the invention may be used to form an electrically-gated single-electron transistor, wherein a gate electrode is provided on the at least one nanoparticle opposite the vertex. In other embodiments, a chemically-gated single-electron transistor may be provided by providing an analyte-specific binding agent on the surface of the at least one nanoparticle.
Single-electron transistors may be fabricated, according to method embodiments of the present invention, by forming a projecting feature on a substrate that projects from a face thereof, forming a first electrode on the substrate face that extends onto the projecting feature, forming a second electrode on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode, and placing at least one nanoparticle on the projecting feature between the first and second electrodes. In some embodiments, the projecting feature is a pyramid including a vertex. A first electrode is formed on a first side of the pyramid, including a first electrode end that extends adjacent the vertex. A second electrode is formed on a second side of the pyramid including a second electrode end that extends adjacent the vertex, and that is spaced apart from the first electrode. At least one nanoparticle is placed on the vertex.
In any of the method embodiments, the projecting feature and/or pyramid may project outwardly away from the face of the substrate and/or inwardly to form a trench in the face of the substrate. In some method embodiments, the first and second electrodes may be provided by directionally depositing a conductive layer. For example, a first directional deposition may form a conductive layer on the first side of the pyramid, and a second directional deposition may form a conductive layer on the second side of the pyramid. Moreover, a plurality of spaced apart projecting features such as pyramids, a plurality of first electrodes and a plurality of second electrodes may be fabricated on a substrate. Self-assembled monolayers, insulating layers, analyte-specific binding agents and/or gate electrodes also may be fabricated. Accordingly, the geometric configuration of a feature may determine the spacing between first and second electrodes, to thereby allow a single-electron transistor to be fabricated using conventional microelectronic processing steps, while allowing high performance and/or high yields.